When high-density current flows through a fine wire included in a semiconductor device having a multilayer wiring structure, movement of electrons disturbs arrangement of atoms (such as cupper atoms or aluminum atoms) constituting the wire, which causes diffusion or migration of the metal atoms. This phenomenon is called electromigration (EM). EM forms voids in the wire, leading to a further increase in the current density and in the temperature. As a result, void formation is accelerated, which may ultimately result in disconnection.
Accordingly, it has been considered that a number of vias has to be increased in proportion to an increase in an amount of current flowing through a wire. More specifically, to suppress EM, interconnections of wide or thick wires that carry a great amount of current are designed to be provided with many vias so as to lower the amount of current per via.
For example, as shown in FIGS. 1A and 1B, a single connection via is used for connecting narrow wires M1L and M3L that are parallel to or orthogonal to one another. On the other hand, the number of vias is increased both in a wire-width direction (W) and a wire-length direction (L) to connect wide or thick parallel wires shown in FIG. 1C. When the wide or thick wires M1L and M3L are orthogonal to one another, the number of vias may be further increased as shown in FIG. 1D.
The current density of current flowing through wires increases as miniaturization of semiconductor devices advances. Thus, an allowable number of vias also tends to increase regarding the same amount of current and the same wire width. The increase in the number of vias is prone to increase diameter of a provided via, which, in turn, reduces a margin between adjacent wires, and thus undesirably causing layers to easily come off.
For the purpose of preventing an interlayer insulating film from coming off or preventing a large-scale integrated circuit (LSI) from being destroyed, a method for reducing the number of electric contacts per area by widening intervals of provided contacts than those decided in a manufacturing process has been suggested (see, for example, Japanese Laid-open Patent Publication No. 2004-158846). This method allows reduction in the number of contacts both in the wire-width direction and in the wire-length direction.
However, since recently available semiconductor devices have a greater allowable current value, a method for simply reducing the number of contacts per area, such as the method disclosed in Japanese Laid-open Patent Publication No. 2004-158846, may not guarantee EM resistance. In addition, the method disclosed in Japanese Laid-open Patent Publication No. 2004-158846 does not consider the direction of current.
In view of a fact that EM is likely to occur at vias arranged in lines at the end where current gathers, e.g., five vias arranged at the left and right ends shown in FIGS. 1C and 1D, in interlayer connections with a via matrix, a configuration of arranging vias along a wire in a line has been suggested (see, for example, Japanese Laid-open Patent Publication No. 3-42856). In this method, although vias are arranged in a line to be parallel to the wire, the number of the vias used for connecting wires on upper and lower layers is not reduced in order to ensure the number of vias corresponding to an amount of flowing current. As a result, since a via-occupying area does not change, disadvantages, such as reduction in a margin between adjacent wires, peeling of an insulating film, and reduction in throughput of the electron beam lithography, still remain.